FPGA/ASIC Design Engineer (KTP Associate)
Hatfield, Hertfordshire and Ziath Ltd, Cambridge
Spot salary in the range of £38,804-£42,915 pa (subject to experience)
Fixed term contract for 13 months
The University of Hertfordshire wishes to recruit an adaptable, highly skilled & qualified engineer to lead and deliver a research project in collaboration with Ziath Ltd. This project will develop and embed a capability in machine learning, image processing and System-on-Chip, with support from academic & company supervisors. The Knowledge Transfer Partnership (KTP) includes an £800 training budget & 10% of your time will be dedicated to your personal development, there is potential for more training budget.
About Ziath Ltd
Ziath specialises in instrumentation control and information management in both the academic and the pharmaceutical/biotech industry sectors with a focus on the application of laboratory automation. It concentrates on managing large sample libraries (compound management, biobanking and sample management) using 2D data matrix tubes. Please visit: http://www.ziath.com/ for more information.
As a KTP Associate you will be employed by the University to work with the company to embed new know-how through this innovation project using research and academic support from the University knowledge base. You will apply your degree through real work and springboard your career. This position forms part of the Knowledge Transfer Partnership (KTP) funded by Innovate UK. Knowledge Transfer Partnerships is a partly government-funded programme to encourage collaboration between businesses and universities in the United Kingdom.
The KTP Associate will be employed on a 13-month contract and will carry out duties at the University in Hatfield and at the Company in Cambridge depending on which aspect of the project is being worked on at the time, majority of time may be at the company.
Main responsibilities and duties
You will undertake research within the scope of the KTP project, establishing a programme of research activity and be responsible for delivery of the KTP work plan, handle data collection and analysis when required, test outcomes in real world solutions and contribute to papers and and do presentations and final project reports.
Skills and experience needed
You will have ddemonstrable research experience at undergraduate level (eg final year project) and knowledge of business functions through employment or study (e.g. industrial placement). You will have experience in developing systems with FPGA or ASIC hardware, writing codes in a suitable programming language such as VERILOG, VHDL, C, C++, Python etc. You will have experience in using mathematics, with Linux operating systems and will have the ability to conduct literature searches in the discipline using appropriate electronic resources
You will have good oral and written communication and be proficient in English. You will be able to plan your own activities, have a methodical approach with attention to detail and have problem-solving abilities and be able to develop innovative and highly efficient solutions to defined problems.
You will have a good first degree or equivalent in Electronic Engineering, Computer Science, or other related subjects. It would be advantageous to have an MSc in Mathematics, Electronic Engineering, Computer Science or a PhD in related subjects.
Informal Contact Details
Helen Podmore at firstname.lastname@example.org
Our vision is to transform lives and UH is committed to Equality, Diversity and Inclusion and building a diverse community. We welcome applications from suitably qualified and eligible candidates regardless of their protected characteristics. We offer a range of employee benefits including generous annual leave and discounted Sports Village memberships, personal and professional development and family-friendly policies. #GoHerts
To apply, please visit our website.
Closing date: 15 December 2021.